Dual-read, single-write register files like the one you're building are a real hardware bottleneck architects fight over: RISC-V hardwires x0 to zero exactly as you do here, while superscalar x86 and ARM cores add extra ports and register renaming purely to avoid stalling on this structure. Choosing 8 versus 16 versus 32 architectural registers is a genuine ISA design tradeoff between instruction encoding density and compiler register pressure.