Simulate Reorder Buffer for Out-of-Order Execution

Commit in Program Order

Out-of-order CPUs execute speculatively but retire instructions in original program order through a Reorder Buffer (ROB). Each entry tracks destination, value readiness, and exception state. Only when an instruction is oldest and complete does it commit to architectural state.

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Role in Speculation

• Execute: results land in ROB and physical registers
• Flush on mispredict: discard tail ROB entries from wrong path
• Precise exceptions: interrupt only at commit boundaries

For example, if a divide-by-zero occurs in the ROB but younger ops already executed, the fault fires only when the divide reaches the ROB head.

For this exercise, you will simulate a small ROB that buffers out-of-order completion and commits in order. This task asks you to model flush on branch mispredict before studying Tomasulo's algorithm.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.