Design a Bytecode Instruction Set

Designing a Bytecode ISA

A virtual machine's instruction set architecture defines what operations exist and how they encode. The first fork every VM author faces is stack-based versus register-based design. Stack VMs keep operands implicit on an evaluation stack; register VMs name explicit slots in each frame.

Stack-Based vs Register-Based

Stack-based designs dominate portable bytecode:

JVM, CPython, WebAssembly: compact opcodes, simple compiler targets
Expression trees map directly: PUSH 5; PUSH 3; ADD leaves 8 on the stack

Lua 5.0+, Dalvik: ADD R1, R2, R3 names sources and destination explicitly
Fewer dispatches per expression, but the compiler must allocate registers

Opcode layout matters early. A single-byte opcode (0-255) plus optional operand bytes is the pattern CPython and your VM will follow. Getting stack effects documented now (ADD pops 2, pushes 1) is what lets the compiler, GC, and JIT plug into a stable contract.

For example, compiling print(5 + 3) might emit PUSH 5; PUSH 3; ADD; PRINT.

For This Exercise

This exercise asks you to document a 16-opcode stack ISA before you implement the interpreter. You will implement opcode tables, stack-effect descriptions, and example sequences that every later task builds on.

Design and document a bytecode instruction set in C.

Requirements:

Define an Opcode enum with all 16 instructions (OP_PUSH through OP_PRINT)
Assign each opcode a unique integer value (0-15)
Implement print_opcode_name() to map opcodes to human-readable names
Create a struct Instruction with opcode and optional operand
Implement print_instruction() to show each instruction with its mnemonic and operand
Print a formatted ISA documentation table showing all opcodes, names, and stack effects
Include a section showing example bytecode sequences (e.g., PUSH 5; PUSH 3; ADD; PRINT)
Show stack state before and after each example instruction
Print a summary comparing stack-based vs register-based designs

Test:

Show the complete opcode table
Show example bytecode sequences
Show stack effects for each instruction

Designing a Bytecode ISA

Stack-Based vs Register-Based

Stack-based designs dominate portable bytecode:

JVM, CPython, WebAssembly: compact opcodes, simple compiler targets
Expression trees map directly: PUSH 5; PUSH 3; ADD leaves 8 on the stack

Lua 5.0+, Dalvik: ADD R1, R2, R3 names sources and destination explicitly
Fewer dispatches per expression, but the compiler must allocate registers

For example, compiling print(5 + 3) might emit PUSH 5; PUSH 3; ADD; PRINT.

For This Exercise

Design and document a bytecode instruction set in C.

Requirements:

Define an Opcode enum with all 16 instructions (OP_PUSH through OP_PRINT)
Assign each opcode a unique integer value (0-15)
Implement print_opcode_name() to map opcodes to human-readable names
Create a struct Instruction with opcode and optional operand
Implement print_instruction() to show each instruction with its mnemonic and operand
Print a formatted ISA documentation table showing all opcodes, names, and stack effects
Include a section showing example bytecode sequences (e.g., PUSH 5; PUSH 3; ADD; PRINT)
Show stack state before and after each example instruction
Print a summary comparing stack-based vs register-based designs

Test:

Show the complete opcode table
Show example bytecode sequences
Show stack effects for each instruction

Topic Overview

Designing a Bytecode ISA

Stack-Based vs Register-Based

For This Exercise

Implementation Task

Progressive Hints

Resources

Open Source

Design a Bytecode Instruction Set

Topic Overview

Designing a Bytecode ISA

Stack-Based vs Register-Based

For This Exercise

Implementation Task

Progressive Hints

Resources

Open Source