Write Same Program in x86-64, ARM64, and RISC-V; Compare

Same Algorithm, Three ISAs

Writing one function in x86-64, ARM64, and RISC-V assembly exposes how ISA design shapes code size, register pressure, and encoding complexity.

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Encoding and Philosophy

• x86-64 (CISC): variable-length instructions (1 to 15 bytes), rich addressing modes, decades of backward compatibility
• ARM64 (RISC): fixed 32-bit encodings, 31 GPRs, load/store architecture, tuned for power efficiency
• RISC-V (RISC): fixed 32-bit base instructions, open royalty-free spec, minimalist opcode space

For example, adding two integers might take three instructions on x86 (move, add, return) but two on ARM and RISC-V because arguments already sit in w0/a0 and w1/a1.

For this exercise, you will implement add_numbers stubs for each architecture and compare instruction counts and byte sizes. This task asks you to connect encoding differences to Apple's Arm transition and LLVM's separate backend code generators.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.