Study RISC-V: Implement Simple RISC-V Emulator for RV32I

RV32I Base Integer ISA

RISC-V defines a modular open ISA. RV32I provides 32 registers (x0 hardwired zero), load/store, branches, and immediate arithmetic. Emulator structure mirrors your toy CPU: fetch, decode, execute.

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Instruction Formats

• R-type: register-register ALU ops
• I-type: immediates, loads, JALR
• S/B/U/J: stores, branches, upper immediates, jumps

For example, ADDI x5, x0, 10 places decimal 10 into x5 using opcode 0x13.

For this exercise, you will implement decode and execute for a subset of RV32I and run small binaries linked for qemu-riscv32 or flat hex images. This task asks you to see how a clean encoding map simplifies decoder tables compared to x86.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.