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Study RISC-V: Implement Simple RISC-V Emulator for RV32I

hard6/8

Understand CISC vs RISC Trade-offs with Benchmarks Understand Privileged Instructions: What Makes an Instruction 'Supervisor Only'

Language

Compiler

2.0s Limit 256MB

Implementation

Implement RISC-V RV32I emulator for base instructions.

Requirements:

Implement 32 registers (x0-x31)
Implement R-type instructions (ADD, SUB, AND, OR, XOR)
Implement I-type instructions (ADDI, LW, SW)
Implement B-type instructions (BEQ)
Execute RISC-V programs
Test with sample code
Show register state

Why This Matters

This RV32I emulator is a miniature version of Spike, the official RISC-V ISA simulator, and QEMU's RISC-V target, both used daily by RISC-V chip vendors like SiFive to validate software before silicon exists. RISC-V's open, royalty-free ISA is why it now powers everything from Western Digital storage controllers to Google's ML accelerators, unlike Arm's licensed core designs.

Hints

0 / 3 revealed

Validation Suite

main.c

Workspace 1.0